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1 40v precision single supply rail-rail output low power operational amplifiers isl28108, isl28208, isl28408 the isl28108, isl28208 and is l28408 are single, dual and quad low power precision amplifiers optimized for single supply applications. these de vices feature a common mode input voltage range extending to 0.5v below the v- rail, a rail-to-rail differential input voltage range for use as a comparator, and rail-to-rail output voltage swing, which make them ideal for single supply applications where input operation at ground is important. added features include low offset voltage, and low temperature drift making them the ideal choice for applications requiring high dc accuracy. the output stage is capable of driving large capacitive loads from rail to rail for excellent adc driving performance. the devices can operate for single or dual supply from 3v (1.5v) to 40v (20v) and are fully characterized at 5v and 15v. the combination of precision, low power, and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. applications for these amplifiers include precision instrumentation, data acquis ition, precision power supply control, and industrial control. the isl28108 single is offered in 8 ld tdfn, soic and msop packages. the isl28208 dual amplifier is offered in 8 ld tdfn, msop, and soic packages. the isl28408 is offered in 14 ld soic package. all devices are offered in standard pin configurations and operate over the extended temperature range to -40c to +125c. features ? single or dual supply, rail-to-rail output and below ground (v-) input capability ? rail-to-rail input differential voltage range for comparator applications ? single supply range . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 40v ? low current consumption (v s = 5v) . . . . . . . . . . . . . . 165a ? low noise voltage . . . . . . . . . . . . . . . . . . . . . . . . . 15.8nv/ hz ? low noise current . . . . . . . . . . . . . . . . . . . . . . . . . . . 80fa/ hz ? low input offset voltage . . . . . . . . . . . . . . . . . . . . . . . . . 230v ? superb temperature drift - voltage offset tc . . . . . . . . . . . . . . . . . . . . . . 0.1v/c, typ ? low input bias current . . . . . . . . . . . . . . . . . . . . . . . -13na typ ? operating temperature range. . . . . . . . . . .-40c to +125c ? no phase reversal applications ? precision instruments ? medical instrumentation ? data acquisition ? power supply control ? industrial process control in- in+ r f r ref + isl28108 +3v v- v+ r in - 10k ? r in + 10k ? - + 100k ? v ref 100k ? v out load r sense single-supply, low-side current sense amplifier gain = 10 to 40v figure 1. typical application circuit figure 2. input offset voltage vs input common mode voltage, v s = 15v v os (v) input common mode voltage (v) -500 -400 -300 -200 -100 0 100 200 300 400 500 13 13.5 14 14.5 15 -16 -15.5 -15 -14.5 -14 +25c +125c v s = 15v -40c july 1, 2011 fn6935.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl28108, isl28208, isl28408 2 fn6935.2 july 1, 2011 pin configurations ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # coming soon isl28108fbz 28108 fbz -40 to +125 8 ld soic m8.15e coming soon isl28108frtz 108z -40 to +125 8 ld tdfn l8.3x3a coming soon isl28108fuz 8108z -40 to +125 8 ld msop m8.118 isl28208fbz 28208 fbz -40 to +125 8 ld soic m8.15e isl28208frtz 208f -40 to +125 8 ld tdfn l8.3x3a coming soon isl28208fuz 8208z -40 to +125 8 ld msop m8.118 coming soon ISL28408FBZ 28408 fbz -40 to +125 14 ld soic m14.15 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic pack aged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-fr ee products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl28108 , isl28208 , isl28408 . for more information on msl please see tech brief tb363 . isl28108 (8 ld tdfn) top view isl28108 (8 ld msop, soic) top view isl28208 (8 ld tdfn) top view isl28208 (8 ld soic, msop top view isl28408 (14 ld soic) top view 2 3 4 1 7 6 5 8 nc -in +in v- nc v+ v out nc + - pad nc -in +in v- 1 2 3 4 8 7 6 5 nc v+ v out nc + - 2 3 4 1 7 6 5 8 v out _a -in_a +in_a v- v+ v out _b -in_b +in_b + - +- pad v out _a -in_a +in_a v- 1 2 3 4 8 7 6 5 v+ v out _b -in_b +in_b + - +- -+ - + -+ - + bc ad v out _ a -in _ a +in _ a v + 1 2 3 4 5 6 7 10 9 8 11 12 13 14 +in _ b -in _ b v out _ b v - +in _ c -in _ c v out _ c v out _ d -in _ d +in _ d
isl28108, isl28208, isl28408 3 fn6935.2 july 1, 2011 pin descriptions isl28108 (8 ld soic, msop, tdfn) isl28208 (8 ld soic, tdfn) isl28408 (14 ld soic, tssop) pin name equivalent circuit description 3 - - +in circuit 1 amplifier non-inverting input -3 3+in_a -5 5+in_b - - 10 +in_c - - 12 +in_d 4 4 11 v- circuit 3 negative power supply 2 - - -in circuit 1 amplifier inverting input -2 2-in_a -6 6-in_b -- 9-in_c --13-in_d 7 8 4 v+ circuit 3 positive power supply 6- -v out circuit 2 amplifier output -1 1v out _a -7 7v out _b -- 8v out _c --14v out _d 1, 5, 8 - - nc - no internal connection pad pad - pad - thermal pad - tdfn and qfn packages only. connect thermal pad to ground or most negative potential. circuit 2 circuit 1 v+ v- circuit 3 capacitively triggered esd clamp in- v+ v- in+ v+ v- out
isl28108, isl28208, isl28408 4 fn6935.2 july 1, 2011 absolute maximum ratings thermal information maximum supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42v maximum differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42v or v - - 0.5v to v + + 0.5v min/max input voltage . . . . . . . . . . . . . . . . . . .42v or v - - 0.5v to v + + 0.5v max/min input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma output short-circuit duration (1 output at a time) . . . . . . . . . . . indefinite esd tolerance human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 6kv machine model (tested per jesd22-a115-c) . . . . . . . . . . . . . . . . . . 400v charged device model (tested per jesd22-c110d) . . . . . . . . . . . . . 2kv thermal resistance (typical) ja (c/w) jc (c/w) 8 ld soic package (108, 208, notes 4, 7) . . 120 55 8 ld tdfn package (108, 208, notes 5, 6). . 47 6 8 ld msop package (108, 208, notes 4, 7) . 150 45 14 ld soic package (408, notes 4, 7). . . . . . - - storage temperature range . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions ambient operating temperature range . . . . . . . . . . . . . . -40c to +125c maximum operating junction temperature . . . . . . . . . . . . . . . . . . +150c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3v (1.5v) to 40v (20v) caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. for jc , the ?case temp? location is taken at the package top center. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v s 15v, v cm = 0, v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +125c. temperature data established by characterization . parameter description conditions min (note 8) typ max (note 8) unit v os input offset voltage -230 25 230 v -330 330 v tcv os input offset voltage temperature coefficient isl28208 soic -40c to +125c 0.1 1.1 v/ c isl28208 tdfn -40c to +125c 0.2 1.4 v/ c v os input offset voltage match (isl28208 only) -300 5 300 v -400 400 v i b input bias current -43 -13 na -63 na tci b input bias current temperature coefficient 0.07 na/ c i os input offset current -3 0 3 na -4 4 na cmrr common-mode rejection ratio v cm = v - -0.5v to v + -1.8v 119 db v cm = v - -0.2v to v + -1.8v 123 db 102 db v cm = v - to v + -1.8v 105 123 db 102 115 db
isl28108, isl28208, isl28408 5 fn6935.2 july 1, 2011 v cmir common mode input voltage range guaranteed by cmrr test v - - 0.5 v + - 1.8 v v - v + - 1.8 v psrr power supply rejection ratio v s = 3v to 40v, v cmir = valid input voltage 110 128 db 109 124 db a vol open-loop gain v o = -13v to +13v, r l = 10k to ground 117 126 db 100 db v ol output voltage low, v out to v - r l = 10k 52 85 mv 145 mv v oh output voltage high, v + to v out r l = 10k 70 110 mv 150 mv i s supply current/amplifier r l = open 185 250 a 270 350 a i sc+ output short circuit source current r l = 10 to v - 19 ma i sc- output short circuit sink current r l = 10 to v + 30 ma v supply supply voltage range guaranteed by psrr 3 40 v ac specifications gbwp gain bandwidth product a cl = 101, v o = 100mv p-p , r l = 2k 1.2 mhz e np-p noise voltage 0.1hz to 10hz; v s = + 18v 580 nvp-p e n noise voltage density f = 10hz; v s = + 18v 18 nv/ hz e n noise voltage density f = 100hz; v s = + 18v 16 nv/ hz e n noise voltage density f = 1khz; v s = + 18v 15.8 nv/ hz e n noise voltage density f = 10khz; v s = + 18v 15.8 nv/ hz i n noise current density f = 10khz; v s = + 18v 80 fa/ hz thd + n total harmonic distortion + noise 1khz, a v = 1, v o = 3.5v rms , r l =10k 0.00042 % transient response sr slew rate, v out 20% to 80% a v = 1, r l = 2k , v o = 10v p-p 0.45 v/s t r , t f , small signal rise time, v out 10% to 90% a v = 1, v out = 100mv p-p , r f = 0 , r l =2k to v cm 264 ns fall time, v out 90% to 10% a v = 1, v out = 100mv p-p , r f = 0 , r l = 2k to v cm 254 ns t s settling time to 0.01% 10v step; 10% to v out a v = -1, v out = 10v p-p , r g = r f =10k, r l =2k to v cm 27 s electrical specifications v s 15v, v cm = 0, v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +125c. temperature data established by characterization . (continued) parameter description conditions min (note 8) typ max (note 8) unit
isl28108, isl28208, isl28408 6 fn6935.2 july 1, 2011 electrical specifications v s 5v, v cm = 0, v o = 0v, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +125c. te mperature data established by characterization . parameter description conditions min (note 8) typ max (note 8) unit v os offset voltage -230 25 230 v -330 330 v tcv os input offset voltage temperature coefficient isl28208 soic -40c to +125c 0.1 1.1 v/ c isl28208 tdfn -40c to +125c 0.2 1.4 v/ c v os input offset voltage match (isl28208 only) -300 3 300 v -400 400 v i b input bias current -43 -15 na -63 na tci b input bias current temperature coefficient -40c to +125c -0.067 na/ c i os input offset current -3 0 3 na -4 4 na cmrr common-mode rejection ratio v cm = v - -0.5v to v + -1.8v 101 db v cm = v - -0.2v to v + -1.8v 123 db 89 db v cm = v - to v + -1.8v 105 123 db 100 112 db v cmir common mode input voltage range guaranteed by cmrr test v - - 0.5 v + - 1.8 v v - v + - 1.8 v psrr power supply rejection ratio v s = 3v to 10v, v cmir = valid input voltage 110 126 db 109 123 db a vol open-loop gain v o = -3v to +3v, r l = 10k to ground 117 124 db 99 db v ol output voltage low, v out to v - r l = 10k 23 38 mv 48 mv v oh output voltage high, v + to v out r l = 10k 30 65 mv 70 mv i s supply current/amplifier r l = open 165 250 a 240 350 a i sc+ output short circuit source current r l = 10 to v - 14 ma i sc- output short circuit sink current r l = 10 to v + 22 ma ac specifications gbw gain bandwidth product a cl = 101, v o = 100mv p-p , r l = 2k 1.2 mhz e np-p noise voltage 0.1hz to 10hz 600 nv p-p e n noise voltage density f = 10hz 18 nv/ hz e n noise voltage density f = 100hz 16 nv/ hz e n noise voltage density f = 1khz 15.8 nv/ hz e n noise voltage density f = 10khz 15.8 nv/ hz i n noise current density f = 10khz 90 fa/ hz
isl28108, isl28208, isl28408 7 fn6935.2 july 1, 2011 transient response sr slew rate, v out 20% to 80% a v = 1, r l = 2k , v o = 4v p-p 0.4 v/s t r , t f , small signal rise time, v out 10% to 90% a v = 1, v out = 100mv p-p , r f = 0 , r l =2k to v cm 264 ns fall time, v out 90% to 10% a v = 1, v out = 100mv p-p , r f = 0 , r l = 2k to v cm 254 ns t s settling time to 0.01% 4v step; 10% to v out a v = -1, v out = 4v p-p , r g = r f =10k, r l =2k to v cm 14.4 s note: 8. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. figure 3. isl28208 input offset voltage distribution, v s = 15v figure 4. isl28208 input offset voltage distribution, v s = 5v figure 5. isl28208 soic tcv os vs number of amplifiers, v s = 15v figure 6. isl28208 soic tcv os vs number of amplifiers, v s = 5v electrical specifications v s 5v, v cm = 0, v o = 0v, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +125c. te mperature data established by characterization . (continued) parameter description conditions min (note 8) typ max (note 8) unit v os (v) n u m b e r o f a m p li fi e r s 0 50 100 150 200 250 300 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 v s = 15v v os (v) n u m b e r o f a m p li fi e r s 0 50 100 150 200 250 300 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 v s = 5v n u m b e r o f a m p li fi e r s tcv os (v/c) 0 2 4 6 8 10 12 14 16 18 20 22 24 - 1 . 1 - 1 . 0 - 0 . 9 - 0 . 8 - 0 . 7 - 0 . 6 - 0 . 5 - 0 . 4 - 0 . 3 - 0 . 2 - 0 . 1 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0 1 . 1 v s = 15v n u m b e r o f a m p l i f i e r s tcv os (v/c) 0 2 4 6 8 10 12 14 16 18 20 22 24 - 1 . 1 - 1 . 0 - 0 . 9 - 0 . 8 - 0 . 7 - 0 . 6 - 0 . 5 - 0 . 4 - 0 . 3 - 0 . 2 - 0 . 1 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0 1 . 1 v s = 5v
isl28108, isl28208, isl28408 8 fn6935.2 july 1, 2011 figure 7. isl28208 tdfn tcv os vs number of amplifiers, v s = 15v figure 8. isl28208 tdfn tcv os vs number of amplifiers, v s = 5v figure 9. v os vs temperature figure 10. i bias vs temperature vs supply figure 11. input offset voltage vs input common mode voltage, v s = 15v figure 12. input offset voltage vs input common mode voltage, v s = 5v typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) n u m b e r o f a m p l i f i e r s tcv os (v/c) 0 2 4 6 8 10 12 14 16 18 20 22 24 - 1 . 1 - 1 . 0 - 0 . 9 - 0 . 8 - 0 . 7 - 0 . 6 - 0 . 5 - 0 . 4 - 0 . 3 - 0 . 2 - 0 . 1 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0 1 . 1 v s = 15v n u m b e r o f a m p l i f i e r s tcv os (v/c) 0 2 4 6 8 10 12 14 16 18 20 22 24 - 1 . 1 - 1 . 0 - 0 . 9 - 0 . 8 - 0 . 7 - 0 . 6 - 0 . 5 - 0 . 4 - 0 . 3 - 0 . 2 - 0 . 1 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0 1 . 1 v s = 5v temperature (c) -40 -20 0 20 40 60 80 100 120 v o s ( v ) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 v s = 5v v s = 2.25v v s = 20v v s = 15v temperature (c) -40 -20 0 20 40 60 80 100 120 i bias (na) -25 -20 -15 -10 -5 0 v s = 5v v s = 15v v s = 21v v s = 1.5v v s = 2.25v v os (v) input common mode voltage (v) -500 -400 -300 -200 -100 0 100 200 300 400 500 13 13.5 14 14.5 15 -16 -15.5 -15 -14.5 -14 +25c +125c v s = 15v -40c v os (v) input common mode voltage (v) -500 -400 -300 -200 -100 0 100 200 300 400 500 3 3.5 4 4.5 5 -6 -5.5 -5 -4.5 -4 +25c +125c v s = 5v -40c
isl28108, isl28208, isl28408 9 fn6935.2 july 1, 2011 figure 13. cmrr vs temperature, v s = 15v figure 14. cmrr vs temperature, v s = 5v figure 15. cmrr vs frequency, v s = 15v figure 16. psrr vs frequency, v s = 5v & 15v figure 17. psrr (dc) vs temperature, v s = 15v figure 18. psrr (dc) vs temperature, v s = 5v typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) temperature (c) -40 -20 0 20 40 60 80 100 120 cmrr (db) 100 105 110 115 120 125 130 v s = 15v channel-a channel-b temperature (c) -40 -20 0 20 40 60 80 100 120 cmrr (db) 100 105 110 115 120 125 130 v s = 5v channel-a channel-b c m r r ( d b ) frequency (hz) 1m 1 10 100 1k 10k 100k 1m 10m 100m 1g 0.1 0.01 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 v s = 15v simulation 10 100 1k 10k 100k 1m 10m p s r r ( d b ) frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 110 120 c l = 4pf v source = 1v p-p r l = 10k a v = 1 v s = 5v, 15v psrr+ psrr- temperature (c) p s r r ( d b ) 120 125 130 135 140 -40 -20 0 20 40 60 80 100 120 v s = 15v temperature (c) p s r r ( d b ) 120 125 130 135 140 -40 -20 0 20 40 60 80 100 120 v s = 5v
isl28108, isl28208, isl28408 10 fn6935.2 july 1, 2011 figure 19. output overhead voltage high vs load current, v s = 5v and 15v figure 20. output overhead voltage low vs load current, v s = 5v and 15v figure 21. isl28208 output volt age swing vs load current v s = 15v figure 22. isl28208 output voltage swing vs load current v s = 5v figure 23. v out high & low vs temperature, v s =15v,r l =10k figure 24. v out high and low vs temperature, v s = 5v, r l = 10k typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) v + - v o h ( v ) load current (ma) 0.001 0.01 0.1 1 0.001 0.01 0.1 1 10 -40c +25c 125c v s = 5v and 15v v o l - v - ( v ) load current (ma) 0.001 0.01 0.1 1 0.001 0.01 0.1 1 10 -40c +25c 125c v s = 5v and 15v v o h ( v ) v o l ( v ) i-force (ma) 11 12 13 14 15 -15 -14 -13 -12 -11 10 -10 v s = 15v a v = 2 v in = 7.5v-dc r f = r g = 100k 0 2 4 6 8 10 12 14 16 18 20 22 24 -40c 0c +25c +75c 125c v o h ( v ) v o l (v ) i-force (ma) v s = 5v a v = 2 v in = 2.5v-dc r f = r g = 100k 0 2 4 6 8 10 12 14 16 18 20 22 24 1 2 3 4 5 -5 -4 -3 -2 -1 -40c 0c +25c 125c +75c temperature (c) -40 -20 0 20 40 60 80 100 120 v o h a n d v o l ( m v ) 0 10 20 30 40 50 60 70 80 90 100 v s = 15v r l = 10k v oh (v + to v out ) v ol (v out to v - ) temperature (c) -40 -20 0 20 40 60 80 100 120 v o h a n d v o l ( m v ) 0 10 20 30 40 50 60 70 80 90 100 v s = 5v r l = 10k v oh (v + to v out ) v ol (v out to v - )
isl28108, isl28208, isl28408 11 fn6935.2 july 1, 2011 figure 25. short circuit current vs temperature, v s =15v figure 26. short circuit current vs temperature, v s = 5v figure 27. max output voltage vs frequency figure 28. no phase reversal figure 29. av ol vs temperature figure 30. open-loop gain, phase vs frequency, v s = 15v typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) i s c ( m a ) 0 5 10 15 20 25 30 35 40 45 50 temperature (c) -40-20 0 20406080100120 v s = 15v r l = 10k i sc -sink i sc -source i s c ( m a ) 0 5 10 15 20 25 30 35 40 45 50 v s = 5v r l = 10k temperature (c) -40-20 0 20406080100120 i sc -sink i sc -source 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1k 10k 100k 1m v o u t ( v p - p ) frequency (hz) v s = 15v a v = 1 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 i n p u t a n d o u t p u t ( v ) time (ms) 01020 2468 12141618 v s = 5v v in = 5.9v input output -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) 100 110 120 130 140 a v o l ( d b ) v s = 15v v s = 5v -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 1 10 100 1k 10k 100k 1m 10m 100m 1g g a i n ( d b ) , p h a s e ( ) frequency (hz) 0.1 v s = 15v r l = 1m ? simulation gain phase
isl28108, isl28208, isl28408 12 fn6935.2 july 1, 2011 figure 31. supply current vs supply voltage figure 32. frequency response vs closed loop gain figure 33. gain vs frequency vs r l , v s = 15v figure 34. gain vs frequency vs r l , v s = 5v figure 35. gain vs frequency vs output voltage figure 36. gain vs frequency vs supply voltage typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) i s u p p l y p e r a m p l i f i e r ( a ) v supply (v) 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 0 2 4 6 8 1012141618202224262830323436384042 -10 0 10 20 30 40 50 60 70 1k 10k 100k 1m 10m g a i n ( d b ) frequency (hz) 100 a cl = 1 a cl = 10 a cl = 1001 v s = 5v, 15v c l = 4pf v out = 100mv p-p r l = 2k a cl = 101 r f = 0, r g = r f = 10k ? , r g = 10 ? r f = 10k ? , r g = 100 ? r f = 10k ? , r g = 1.1k ? frequency (hz) normalized gain (db) 100k 1m 10m 10k 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 r l = 100 r l = 49.9 r l = 499 v s = 15v a v = +1 v out = 100mv p-p c l = 4pf 100 r l = open, 100k, 10k r l = 1k frequency (hz) normalized gain (db) 100k 1m 10m 10k 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100 v s = 5v a v = +1 v out = 100mv p-p c l = 4pf r l = 100 r l = 49.9 r l = 499 r l = open, 100k, 10k r l = 1k frequency (hz) normalized gain (db) 100k 1m 10m 10k 1k - -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100 v s = 5v a v = +1 r l = inf c l = 4pf v out = 50mv p-p v out = 10mv p-p v out = 100mv p-p v out = 500mv p-p v out = 1v p-p normalized gain (db) frequency (hz) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100 1k 10k 100k 1m 10m c l = 4pf r l = 10k a v = +1 v out = 100mv p-p v s = 15v v s = 5v v s = 20v v s = 2.5v
isl28108, isl28208, isl28408 13 fn6935.2 july 1, 2011 figure 37. output impedance vs frequency, v s = 15v figure 38. output impedance vs frequency, v s = 5v figure 39. input noise voltage (en) and current (in) vs frequency, v s = 18v figure 40. input noise voltage (en) and current (in) vs frequency, v s = 5v figure 41. input noise voltage 0.1hz to 10hz, v s = 18v figure 42. input noise voltage 0.1hz to 10hz, v s = 5v typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) 0.01 0.10 1 10 100 10 100 1k 10k 100k 1m 10m z ou t ( ? ) frequency (hz) 1 v s = 15v g = 1 g = 10 g = 100 0.01 0.10 1 10 100 10 100 1k 10k 100k 1m 10m z ou t ( ? ) frequency (hz) 1 v s = 5v g = 1 g = 10 g = 100 0.1 1 10 100 1k 10k 100k i n p u t n o i s e v o l t a g e ( n v / h z ) frequency (hz) i n p u t n o i s e c u r r e n t ( p a / h z ) 0.01 0.1 1 10 100 v s = 18v 0.01 0.1 1 10 100 input noise voltage input noise current 0.1 1 10 100 1k 10k 100k i n p u t n o i s e v o l t a g e ( n v / h z ) frequency (hz) i n p u t n o i s e c u r r e n t ( p a / h z ) 0.01 0.1 1 10 100 v s = 5v 0.01 0.1 1 10 100 input noise voltage input noise current i n p u t n o i s e v o lta g e ( nv ) 012345678910 time (s) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 v s = 18v a v = 10k i n p u t n o i s e v o lta g e ( nv ) 012345678910 time (s) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 v s = 5v a v = 10k
isl28108, isl28208, isl28408 14 fn6935.2 july 1, 2011 figure 43. isl28208 channel separation vs frequency, v s = 5v, 15v figure 44. positive output overload response time, v s =15v figure 45. negative output overload response time, v s =15v figure 46. positive output overload response time, v s = 5v figure 47. negative output overload response time, v s =5v typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) 10 100 1k 10k 100k 1m 10m c r o s s t a l k ( d b ) frequency (hz) 0 20 40 60 80 100 120 140 160 v s = 15v c l = 4pf v tx = 1v p-p r l _ transmit = r l _ receive = 10k r l _ transmit = 2k r l _ receive = 10k o u t p u t ( v ) i n p u t ( m v ) time (s) 0 4 8 12 16 20 0 40 80 120 160 200 0 20 40 60 80 100 120 140 160 180 200 v s = 15v a v = 100 v in = 100mv p-p overdrive = 1v r l = 10k output input o u t p u t ( v ) i n p u t ( m v ) time (s) 0 20 40 60 80 100 120 140 160 180 200 v s = 15v a v = 100 v in = 100mv p-p overdrive = 1v r l = 10k -20 -16 -12 -8 -4 0 -200 -160 -120 -80 -40 0 input output o u t p u t ( v ) i n p u t ( m v ) time (s) 0 1 2 3 4 5 6 0 10 20 30 40 50 60 v s = 5v a v = 100 v in = 50mv p-p overdrive = 1v r l = 10k 0 20 40 60 80 100 120 140 160 180 200 output input o u t p u t ( v ) i n p u t ( m v ) time (s) -6 -5 -4 -3 -2 -1 0 -60 -50 -40 -30 -20 -10 0 v s = 5v a v = 100 v in = 50mv p-p overdrive = 1v r l = 10k 0 20 40 60 80 100 120 140 160 180 200 input output
isl28108, isl28208, isl28408 15 fn6935.2 july 1, 2011 figure 48. overshoot vs capacitive load, v s = 15v figure 49. overshoot vs capacitive load, v s =5v figure 50. large signal 10v step response, v s = 15v figure 51. large signal 4v step response, v s = 5v figure 52. small signal transient response v s = 5v, 15v typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) o v e r s h o o t ( % ) load capacitance (nf) 0 10 20 30 40 50 60 0.001 0.010 0.100 1 10 100 v s = 15v v out = 100mv p-p a v = 10 a v = 1 a v = -1 o v e r s h o o t ( % ) load capacitance (nf) 0 10 20 30 40 50 60 0.001 0.010 0.100 1 10 100 v s = 5v v out = 100mv p-p a v = 10 a v = 1 a v = -1 -6 -4 -2 0 2 4 6 v o u t ( v ) time (s) 0 100 200 300 400 v s = 15v a v = 1 r l = 2k c l = 4pf 0 v o u t ( v ) time (s) -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 2.4 100 200 300 400 v s = 5v a v = 1 r l = 2k c l = 4pf v o u t ( m v ) time (s) -100 -80 -60 -40 -20 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v s = 15v a v = 1 r l = 2k c l = 4pf v s = 5v and
isl28108, isl28208, isl28408 16 fn6935.2 july 1, 2011 applications information functional description the isl28108, isl28208, and isl28408 are single, dual and quad, 1.2mhz, single supply rail-to-rail output amplifiers with a common mode input voltage range extending to a range of 0.5v below the v- rail. their input stages are optimized for precision sensing of ground referenced sign als in low voltage, single supply applications. the input stage has the capability of handling large input differential voltages without phase inversion making them suitable for high voltage compar ator applications. their bipolar design features high open loop gain and excellent dc input and output temperature stability. these op amps feature low quiescent current of 165a, and a maximum low temperature drift of only 1.1v/c for the isl28208 in the soic package and 1.4v/c for the isl28208 in the tdfn package (s ee figures 7 and 8). both devices are fabricated in a new precision 40v complementary bipolar di process and immune from latch-up. operating voltage range the devices are designed to operate over the 3v (1.5v) to 40v (20v) range and are fully characterized at 5v and 15v. both dc and ac performance remain virtua lly unchanged over the 5v to 15v operating voltage range. parameter variation with operating voltage is shown in the ?typical performance curves? beginning on page 7. input stage performance the pnp input stage has a common mode input range extending up to 0.5v below ground at +25c (see figures 11 and 12). full amplifier performance is guaranteed down to ground (v-) over the - 40c to +125c temperature range. for common mode voltages down to -0.5v the amplifiers are fully functional, but performance degrades slightly over the full temperature range. this feature provides excellent cmrr, ac performance and dc accuracy when amplifying low level ground referenced signals. the input stage has a maximum input differential voltage equal to a diode drop greater than th e supply voltage (max 42v) and does not contain the back-to-back input protection diodes found on many similar amplifiers. this feature enables the device to function as a precision comparator by maintaining very high input impedance for high voltage differential input comparator voltages. the high differential input impedance also enables the device to operate reliably in large signal pulse applications without the need for anti-paral lel clamp diodes required on mosfet and most bipolar inpu t stage op amps. thus, input signal distortion caused by nonlinear clamps under high slew rate conditions are avoided. in applications where one or both amplifier input terminals are at risk of exposure to voltages beyond the supply rails, current limiting resistors may be needed at each input terminal (see figure 53 r in +, r in -) to limit current through the power supply esd diodes to 20ma. output drive capability the bipolar rail-to-rail output stag e features low saturation levels that enable an output voltage sw ing to less than 10mv when the total output load (including feedback resistance) is held below 50a (figures 19 and 20). with 15v supplies this can be achieved by using feedback resistor values >300k ? . the low input bias and offset currents (-43na and 3na +25c max respectively) minimize dc offset errors at these high resistance values. for example, a balanced 4 resistor gain circuit (figure 53) with 1m ? feedback resistors (r f , r g ) generates a worst case input offset error of only 3mv. furthermore, the low noise current reduces the added noise associated with high feedback resistance. the output stage is internally current limited. output current limit over-temperature is shown in figures 25 and 26. the amplifiers can withstand a short circuit to ei ther rail as long as the power dissipation limits are not exceeded. this applies to only one amplifier at a time fo r the dual op amp. continuous operation under these conditions may degrade long-term reliability. the amplifiers perform well driving capacitive loads (figures 48 and 49). the unity gain, voltage follower (buffer) configuration provides the highest bandwidth, bu t is also the most sensitive to ringing produced by load capacitance found in bnc cables. unity gain overshoot is limited to 30% at capacitance values to 0.33nf. at gains of 10 and higher, the de vice is capable of driving more than 10nf without significant overshoot. output phase reversal output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. these devices are immune to output phase reversal, out to 0.5v beyond the rail (v abs max ) limit (see figure 28). figure 53. input esd diode current limiting - + r in - r l v in - v+ v- r in + v in + r f r g
isl28108, isl28208, isl28408 17 fn6935.2 july 1, 2011 using only one channel if the application only requires one channel, the user must configure the unused channel to prevent it from oscillating. the unused channel will oscillate if the input and output pins are floating. this will result in high er than expected supply currents and possible noise injection into the channel being used. the proper way to prevent this oscillation, is to short the output to the inverting input and ground the positive input (as shown in figure 54). power dissipation it is possible to exceed the +150c maximum junction temperatures under certain load and power supply conditions. it is therefore important to ca lculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions , or package type need to be modified to remain in the safe operating area. these parameters are related using equation 1: where: ?p dmaxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) ?pd max for each amplifier can be calculated using equation 2: where: ?t max = maximum ambient temperature ? ja = thermal resistance of the package ?pd max = maximum power dissipation of 1 amplifier ?v s = total supply voltage ?i qmax = maximum quiescent supply current of 1 amplifier ?v outmax = maximum output voltage swing of the application ?r l = load resistance isl28108, isl28208, isl28408 spice model figure 55 shows the spice model schematic and figure 56 shows the net list for the spice model. the model is a simplified version of the actual device and simulates important ac and dc parameters. ac parameters incorporated into the model are: 1/f and flatband noise voltage, slew rate, cmrr, gain and phase. the dc parameters are i os , total supply current and output voltage swing. the model uses typical parameters given in the ?electrical specifications? table beginning on page 4. the avol is adjusted for 122db with the dominant pole at 1hz. the cmrr is set 128db, f = 6khz. the input stage models th e actual device to present an accurate ac representation. the model is configured for ambient temperature of +25c. figures 57 through 71 show the characterization vs simulation results for the noise voltage, open loop gain phase, closed loop gain vs frequency, gain vs freq uency vs rl, cmrr, large signal 10v step response, small signal 0.05v step and output voltage swing 15v supplies. license statement the information in this spice model is protected under the united states copyright laws. intersil corporation hereby grants users of this macro-model hereto referred to as ?licensee?, a nonexclusive, nontransferable licence to use this model as long as the licensee abides by the terms of this agreement. before using this macro-model, the licensee should read this license. if the licensee does not accept these terms, permission to use the model is not granted. the licensee may not sell, loan, rent, or license the macro- model, in whole, in part, or in modified form, to anyone outside the licensee?s company. the licensee may modify the macro- model to suit his/her specific applications, and the licensee may make copies of this macro-mode l for use within their company only. this macro-model is provided ?as is, where is, and with no warranty of any kind either expressed or implied, including buy not limited to any implied warranties of merchantability and fitness for a particular purpose.? in no event will intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. intersil reserves the right to make changes to the product and the macro-model without prior notice. figure 54. preventing oscillations in unused channels - + t jmax t max ja xpd maxtotal + = (eq. 1) pd max v s i qmax v s ( - v outmax ) v outmax r l ------------------------ + = (eq. 2)
isl28108, isl28208, isl28408 18 fn6935.2 july 1, 2011 common mode gain stage with zero correction current sources output stage input stage 1st gain stage mid supply ref v 2nd gain stage vc vmid vmid vmid 13 26 v- 2 15 20 v++ v-- 19 27 v++ vout 5 14 23 vmid v-- v++ v-- 6 17 v+ vg 16 11 vin+ 8 v-- 10 7 9 22 21 24 18 vc 25 1 28 v++ 12 vin- 0 0 0 0 + - g1 gain = 0.477 - + + - eos e gain = 1 eos e gain = 1 + - g15 gain = 314.15e-6 cindif 1.21e-12 q8 pnp_lateral q8 + - g8 gain = 0.6 c6 10e-12 r11 1e-3 ios 3e-9 r5 1 1 dx d11 r13 3.183e3 r13 c2 2.31e-11 d1 dbreak d1 dbreak r7 7.62e9 dx d3 v2 -6.76 - + + - e4 gain = 0.5 + - g7 gain = 0.6 gain = 0.6 + - g5 gain = 0.6 i2 6e-6 c3 10e-12 c3 10e-12 v4 -6.76 dx d8 + - g16 gain = 314.15e-6 dy d12 + - g13 gain = 12.5e-3 r19 3.183e3 q9 pnp_lateral q9 pnp_lateral + - g11 gain = 12.5e-3 + - g2 gain = 0.477 + - g3 gain = 261.74e-6 r4 6250 dx d10 dn d14 r15 80 r8 7.62e9 l1 1.59e-08 c5 10e-12 c5 10e-12 v5 -0.4 v5 -0.4 r9 1e-3 dn d13 v3 -6.74 - + + - e3 gain = 1 + - g9 gain = 314.15e-6 l3 1.59e-08 r3 6250 v6 -0.4 v6 cin2 4.19e-12 dx d4 + - g12 gain = 12.5e-3 q7 pnp_input q7 i3 6e-6 + - g6 gain = 0.6 dx r1 5e11 r14 3.183e3 r12 1e-3 c4 10e-12 c4 10e-12 dx d7 - + + - gain = 0.3 dy d9 q6 pnp_input r10 1e-3 - + + - e2 gain = 1 e2 + - g4 gain = 261.74e-6 1150 i1 12e-6 + - g14 gain = 12.5e-3 l4 1.59e-08 dx d5 d2 dbreak d2 dbreak r6 1 l2 1.59e-08 isy 185e-6 isy r16 80 v1 -6.74 r20 3.183e3 + - g10 gain = 314.15e-6 c1 2.31e-11 r2 v7 0.1 0.1 cin1 4.19e-12 figure 55. spice model schematic
isl28108, isl28208, isl28408 19 fn6935.2 july 1, 2011 *isl28108_208 macromodel - covers following *products *isl28108 *isl28208 *isl28408 * *revision history: * revision a, lafontaine march 5th 2011 * model for noise, supply currents, cmrr *128db f=6khz ,avol 122db f=1hz * sr = 0.45v/us, gbwp 1.2mhz. *copyright 2011 by intersil corporation *refer to data sheet "license statement" *use of this model indicates your acceptance *with the terms and provisions in the license *statement. * *intended use: *this pspice macromodel is intended to give *typical dc and ac performance characteristics *under a wide range of external circuit *configurations using compatible simulation *platforms ? such as isim pe. * *device performance features supported by this *model *typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *open and closed loop i/o impedances, *open loop gain and phase, *closed loop bandwidth and frequency *response, *loading effects on closed loop frequency *response, *input noise terms including 1/f effects, *slew rate, *input and output headroom limits to i/o *voltage swing, *supply current at nominal specified supply *voltages. * *device performance features not supported *by this model: *harmonic distortion effects, *output current limiting (current will limit at *40ma), *disable operation (if any), *thermal effects and/or over temperature *parameter variation, *limited performance variation vs. supply *voltage is modeled, *part to part performance variation due to *normal process parameter spread, *any performance difference arising from *different packaging source, *load current reflected into the power supply *current. * * connections: +input * | -input * | | +vsupply * | | | -vsupply * | | | | output * | | | | .subckt isl28108_208 vin+ vin-v+ v- vout * source isl28118_218_subckt_check_0 * *voltage noise e_en vin+ 6 2 0 0.3 d_d13 1 2 dn d_d14 1 2 dn v_v7 1 0 0.1 r_r17 2 0 1150 * *input stage q_q6 11 10 9 pnp_input q_q7 8 7 9 pnp_input q_q8 v-- vin- 7 pnp_lateral q_q9 v-- 12 10 pnp_lateral i_i1 v++ 9 dc 12e-6 i_i2 v++ 7 dc 6e-6 i_i3 v++ 10 dc 6e-6 i_ios 6 vin- dc 3e-9 *d_d1 7 10 dbreak *d_d2 10 7 dbreak r_r1 5 6 5e11 r_r2 vin- 5 5e11 r_r3 v-- 8 6250 r_r4 v-- 11 6250 c_cin1 v-- vin- 4.19e-12 c_cin2 v-- 6 4.19e-12 c_cindif 6 vin- 1.21e-12 * *1st gain stage g_g1 v++ 14 8 11 0.4779867 g_g2 v-- 14 8 11 0.4779867 v_v1 13 14 -6.74 v_v2 14 15 -6.76 d_d3 13 v++ dx d_d4 v-- 15 dx r_r5 14 v++ 1 r_r6 v-- 14 1 * *2nd gain stage g_g3 v++ vg 14 vmid 261.748e-6 g_g4 v-- vg 14 vmid 261.748e-6 v_v3 16 vg -6.74 v_v4 vg 17 -6.76 d_d5 16 v++ dx d_d6 v-- 17 dx r_r7 vg v++ 7.62283e9 r_r8 v-- vg 7.62283e9 c_c1 vg v++ 2.31e-11 c_c2 v-- vg 2.31e-11 * *mid supply ref e_e2 v++ 0 v+ 0 1 e_e3 v-- 0 v- 0 1 e_e4 vmid v-- v++ v-- 0.5 i_isy v+ v- dc 185e-6 * *common mode gain stage with zero g_g5 v++ 19 5 vmid 0.6 g_g6 v-- 19 5 vmid 0.6 g_g7 v++ vc 19 vmid 0.6 g_g8 v-- vc 19 vmid 0.6 e_eos 12 6 vc vmid 1 l_l1 18 v++ 1.59159e-08 l_l2 20 v-- 1.59159e-08 l_l3 21 v++ 1.59159e-08 l_l4 22 v-- 1.59159e-08 r_r9 19 18 1e-3 r_r10 20 19 1e-3 r_r11 vc 21 1e-3 r_r12 22 vc 1e-3 * *pole satge g_g15 v++ 28 vg vmid 314.15e-6 g_g16 v-- 28 vg vmid 314.15e-6 r_r19 28 v++ 3.18319e3 r_r20 v-- 28 3.18319e3 c_c5 28 v++ 10e-12 c_c6 v-- 28 10e-12 * g_g9 v++ 23 28 vmid 314.15e-6 g_g10 v-- 23 28 vmid 314.15e-6 r_r13 23 v++ 3.18319e3 r_r14 v-- 23 3.18319e3 c_c3 23 v++ 10e-12 c_c4 v-- 23 10e-12 * *output stage with correction current sources g_g11 26 v-- vout 23 12.5e-3 g_g12 27 v-- 23 vout 12.5e-3 g_g13 vout v++ v++ 23 12.5e-3 g_g14 v-- vout 23 v-- 12.5e-3 d_d7 23 24 dx d_d8 25 23 dx d_d9 v-- 26 dy d_d10 v++ 26 dx d_d11 v++ 27 dx d_d12 v-- 27 dy v_v5 24 vout -0.4 v_v6 vout 25 -0.4 r_r15 vout v++ 80 r_r16 v-- vout 80 .model pnp_lateral pnp(is=1e-016 bf=250 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model pnp_input pnp(is=1e-016 bf=100 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model dbreak d(bv=43 rs=1) .model dn d(kf=6.69e-9 af=1) .model dx d(is=1e-12 rs=0.1) .model dy d(is=1e-15 bv=50 rs=1) .ends isl28108_208 figure 56. spice net list
isl28108, isl28208, isl28408 20 fn6935.2 july 1, 2011 characterization vs simulation results figure 57. characterized input noise voltage figure 58. simulated input noise voltage figure 59. characterized open-loop gain, phase vs frequency figure 60. simulated open-loop gain, phase vs frequency figure 61. characterized closed loop gain vs frequency figure 62. simulated closed loop gain vs frequency 10 100 0.1 1 10 100 1k 10k 100k i n p u t n o i s e v o l t a g e ( n v / h z ) frequency (hz) 100 0.1 1 10 100 1k 10k 100k i n p u t n o i s e v o l t a g e ( n v / h z ) frequency (hz) 10 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 1 10 100 1k 10k 100k 1m 10m 100m 1g g a i n ( d b ) , p h a s e ( ) frequency (hz) 0.1 v s = 15v r l = 1m ? simulation gain phase -100 -50 0 50 100 150 200 1 10 100 1k 10k 100k 1m 10m 100m 1g g a i n ( d b ) , p h a s e ( ) frequency (hz) 0.1 v s = 15v r l = 1m ? simulation gain phase -10 0 10 20 30 40 50 60 70 1k 10k 100k 1m 10m g a i n ( d b ) frequency (hz) 100 a cl = 1 a cl = 10 a cl = 1001 v s = 5v, 15v c l = 4pf v out = 100mv p-p r l = 2k a cl = 101 r f = 0, r g = r f = 10k ? , r g = 10 ? r f = 10k ? , r g = 100 ? r f = 10k ? , r g = 1.1k ? -10 0 10 20 30 40 50 60 70 1k 10k 100k 1m 10m g a i n ( d b ) frequency (hz) 100 v s = 5v, 15v c l = 4pf v out = 100mv p-p r l = 2k r f = 0, r g = r f = 10k ? , r g = 10 ? r f = 10k ? , r g = 100 ? r f = 10k ? , r g = 1.1k ?
isl28108, isl28208, isl28408 21 fn6935.2 july 1, 2011 figure 63. characterized gain vs frequency vs r l figure 64. simulated gain vs frequency vs r l figure 65. characterized cmrr vs freque ncy figure 66. simulated cmrr vs frequency figure 67. characterized large signal 10v step response figure 68. simulated large signal 10v step response characterization vs simulation results (continued) frequency (hz) normalized gain (db) 100k 1m 10m 10k 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 r l = 100 r l = 49.9 r l = 499 v s = 15v a v = +1 v out = 100mv p-p c l = 4pf 100 r l = open, 100k, 10k r l = 1k frequency (hz) normalized gain (db) 100k 1m 10m 10k 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 r l = 100 r l = 49.9 r l = 499 v s = 15v a v = +1 v out = 100mv p-p c l = 4pf 100 r l = open, 100k, 10k r l = 1k c m r r ( d b ) frequency (hz) 1m 1 10 100 1k 10k 100k 1m 10m 100m 1g 0.1 0.01 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 v s = 15v simulation 0 50 100 150 c m r r ( d b ) frequency (hz) 1m 1 10 100 1k 10k 100k 1m 10m 100m 1g 0.1 0.01 v s = 15v simulation -6 -4 -2 0 2 4 6 v o u t ( v ) time (s) 0 100 200 300 400 v s = 15v a v = 1 r l = 2k c l = 4pf -6 -4 -2 0 2 4 6 v o u t ( v ) time (s) 0 100 200 300 400 v s = 15v a v = 1 r l = 2k c l = 4pf
isl28108, isl28208, isl28408 22 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6935.2 july 1, 2011 for additional products, see www.intersil.com/product_tree figure 69. characterized small signal transient response figure 70. simulated small signal transient response figure 71. simulated output voltage swing characterization vs simulation results (continued) v o u t ( m v ) time (s) -100 -80 -60 -40 -20 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v s = 15v a v = 1 r l = 2k c l = 4pf v s = 5v and v o u t ( m v ) time (s) -100 -80 -60 -40 -20 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v s = 15v a v = 1 r l = 2k c l = 4pf v s = 5v and 0 0.5 1.0 1.5 2.0 -20v -10v 0v 10v 20v o u t p u t v o l t a g e s w i n g ( v ) time (m s) voh = 14.93v vol = -14.94v
isl28108, isl28208, isl28408 23 fn6935.2 july 1, 2011 products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl28108 , isl28208 , isl28408 . to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 4/20/11 fn6935.2 ? added discussion of isl28408 throughout datasheet. ? on page 2 in ?ordering information?: added new pa rt, ?ISL28408FBZ?. corrected part marking for isl28208frtz from 208z to 208f. added ?isl28408? to note 3. under? pin configurations,? added isl28408 (14 ld soic) pi n configuration diagram. ? on page 3: in pin descriptions table, added column for isl28408 14ld soic. corrected schematic for circuit 2. ? on page 4: under ?thermal information? added " 14 ld soic package (408, notes 4, 7)" and added isl28108 to 8 ld tdfn and 8 ld msop. changed ja and jc for 8 ld tdfn package from 48 and 5.5 to 47 and 6. added note 6 regarding jc ?case temp? measurement, and applied it to 8 ld tdfn package. ? on page 4: in electrical specificatio ns table, changed typ spec for tci b from 70 pa/ c to 0.07na/ c. on page 6, change typ spec for tci b from -67 pa/ c to -0.067na/ c. these are not spec changes since the values are the same. ? on page 10, figs. 19 and 20: changed y axis units label from (mv) to (v); changed x axis units label from (a) to (ma). ? on page 16, under ?output drive capability,? para 2, changed "the output stage can swing at moderate levels of output current (figures 21 and 22) and the outp ut stage is internally current limited. output current limit over-termperature..." to "the output stage is internally current limited. output current limit over- temperature..." 3/11/11 fn6935.1 ? on page 1, in the first paragraph - added the following after v-rail: "a rail-to-rail differential input voltag e range for use as a comparator,?" ?on page1 in ?features: - added bullet - ?rail-to-rail input differenti al voltage range for comparator applications? - changed low noise current from "100 fa/sq.root hz" to "80fa/sq.root hz" ? on page 2 in ?ordering information? - removed "c oming soon" from isl28208frtz part since it is releasing. ? on page 4, changed ?esd tolerance? as follows: - human body model changed from "3kv" to "6kv" - machine model changed from "300v" to "400v" - added jedec test information for all esd ratings ? on page 4 and page 6, added test conditions for soic tcvos specs. added tcvos specs for tdfn. ? on page 5 changed ?noise current density? typical from "100" to "80" ? on page 16, updated applications information functional description ? on page 16 updated input stage performance section ? on page 16 updated output drive capability section ? on page 17 added isl28108 and isl28208 spice model and license agreement section ? on page 18 added spice net list ? on page 20 added characterization vs simulation results curves 2/16/11 fn6935.0 initial release
isl28108, isl28208, isl28408 24 fn6935.2 july 1, 2011 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise specified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view ?a typical recommended land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view ?b?
isl28108, isl28208, isl28408 25 fn6935.2 july 1, 2011 package outline drawing l8.3x3a 8 lead thin dual flat no-lead plastic package rev 4, 2/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.20mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 6x 0.65 1.50 0.10 8 1 8x 0.30 0.10 6 0.75 0.05 see detail "x" 0.08 0.10 c c c ( 2.90 ) (1.50) ( 8 x 0.30) ( 8x 0.50) ( 2.30) ( 1.95) 2.30 0.10 0.10 8x 0.30 0.05 a mc b 4 2x 1.950 (6x 0.65) index area pin 1 compliant to jedec mo-229 weec-2 except for the foot length. 7.
isl28108, isl28208, isl28408 26 fn6935.2 july 1, 2011 package outline drawing m8.118 8 lead mini small outline plastic package rev 3, 3/10 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.25 - 0.036 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 8 0.85010 seating plane a 0.65 bsc 3.00.05 4.90.15 (0.40) (1.40) (0.65) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-aa plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m

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